Improper Handling of Faults that Lead to Instruction Skips
Improper Handling of Faults that Lead to Instruction Skips
CWE-1332
Short description
Extended description
The operating conditions of hardware may change in ways that cause unexpected behavior to occur, including the skipping of security-critical CPU instructions. Generally, this can occur due to electrical disturbances or when the device operates outside of its expected conditions.
In practice, application code may contain conditional branches that are security-sensitive (e.g., accepting or rejecting a user-provided password). These conditional branches are typically implemented by a single conditional branch instruction in the program binary which, if skipped, may lead to effectively flipping the branch condition - i.e., causing the wrong security-sensitive branch to be taken. This affects processes such as firmware authentication, password verification, and other security-sensitive decision points.
Attackers can use fault injection techniques to alter the operating conditions of hardware so that security-critical instructions are skipped more frequently or more reliably than they would in a "natural" setting.
Best practices to prevent this CWE
Phase: Architecture and Design
Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.
Phase: Architecture and Design
Design strategies for ensuring safe behavior if instructions attempt to be skipped.
Phase: Architecture and Design
Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.
Phase: Implementation
Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.
Phase: Implementation
Use redundant operations or canaries to detect and respond to faults.
Phase: Implementation
Ensure that fault mitigations are strong enough in practice. For example, a low power detection mechanism that takes 50 clock cycles to trigger at lower voltages may be an insufficient security mechanism if the instruction counter has already progressed with no other CPU activity occurring.
