Incorrect Chaining or Granularity of Debug Components

For debugging and troubleshooting a chip, several hardware design elements are often implemented, including:

Logic errors during design or synthesis could misconfigure the interconnection of the debug components, which could allow unintended access permissions.

• Various Test Access Ports (TAPs) allow boundary scan commands to be executed.
• For scanning the internal components of a chip, there are scan cells that allow the chip to be used as a "stimulus and response" mechanism.
• Chipmakers might create custom methods to observe the internal components of their chips by placing various tracing hubs within their chip and creating hierarchical or interconnected structures among those hubs.